
Sapphicon offers a range of semiconductor processes based on Silicon-on-Sapphire technology. These are available either on a semiconductor fabrication foundry basis, or via our low cost prototype Compressed Reticle service.
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Click here to find out more about Silicon-on-Sapphire performance advantages.
If you design RF or mixed signal/analog circuits check out whether these may be a useful alternative to the traditional Bulk CMOS or III-V semiconductor processes that you currently use.
The following are the Silicon-on-Sapphire semiconductor processes that are available.
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|
Process |
Mask Layers |
Description |
|
|
FA |
3LM 1P |
16 |
0.5 µm SPTM |
|
|
FC |
3LM 1P |
17 |
0.5 µm SPTM thick metal + capacitors |
|
|
FD |
2LM 1P |
14 |
0.5 µm SPDM |
|
|
GA |
3LM 1P |
18 |
0.25 µm SPTM |
|
|
GC |
3LM 1P |
19 |
0.25 µm SPTM thick metal + capacitors |
|
|
GD |
2LM 1P |
16 |
0.25µm SPDM |
|
How to make use of the Foundry Services.
• Sapphicon provides a process design kit for the SoS process.
• Customer carries out the chip design or uses Sapphicon supplied design services.
• GDSII layout data is supplied to Sapphicon for final design rule checking and mask fabrication.
• Sapphicon prepares mask data and sources the mask tooling.
• Devices are supplied either as complete unsawn, wafers or packaged in a variety of prototype packages. Wafers are tested electrically. No functional verification is carried out.
• Packaged devices can be supplied, tested using either a customer or Sapphicon generated test program.